Index: drivers/ide/ide-cs.c =================================================================== RCS file: /home/cvs/linux-nanoengine/drivers/ide/ide-cs.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- drivers/ide/ide-cs.c 9 May 2002 15:41:36 -0000 1.1.1.1 +++ drivers/ide/ide-cs.c 10 Sep 2002 20:39:12 -0000 1.2 @@ -319,10 +319,13 @@ CS_CHECK(RequestIRQ, handle, &link->irq); CS_CHECK(RequestConfiguration, handle, &link->conf); + +#if 0 /* not needed on strongarm */ /* deal with brain dead IDE resource management */ release_region(link->io.BasePort1, link->io.NumPorts1); if (link->io.NumPorts2) release_region(link->io.BasePort2, link->io.NumPorts2); +#endif /* retry registration in case device is still spinning up */ for (i = 0; i < 10; i++) { Index: drivers/pcmcia/Makefile =================================================================== RCS file: /home/cvs/linux-nanoengine/drivers/pcmcia/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- drivers/pcmcia/Makefile 9 May 2002 15:41:51 -0000 1.1.1.1 +++ drivers/pcmcia/Makefile 9 May 2002 17:41:41 -0000 1.2 @@ -72,6 +72,7 @@ sa1100_cs-objs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o sa1100_cs-objs-$(CONFIG_SA1100_GRAPHICSMASTER) += sa1100_graphicsmaster.o sa1100_cs-objs-$(CONFIG_SA1100_ADSBITSY) += sa1100_adsbitsy.o +sa1100_cs-objs-$(CONFIG_SA1100_NANOENGINE) += sa1100_nanoengine.o include $(TOPDIR)/Rules.make Index: drivers/pcmcia/sa1100.h =================================================================== RCS file: /home/cvs/linux-nanoengine/drivers/pcmcia/sa1100.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- drivers/pcmcia/sa1100.h 9 May 2002 15:41:51 -0000 1.1.1.1 +++ drivers/pcmcia/sa1100.h 9 May 2002 17:41:41 -0000 1.2 @@ -197,5 +197,6 @@ extern struct pcmcia_low_level simpad_pcmcia_ops; extern struct pcmcia_low_level graphicsmaster_pcmcia_ops; extern struct pcmcia_low_level adsbitsy_pcmcia_ops; +extern struct pcmcia_low_level nanoengine_pcmcia_ops; #endif /* !defined(_PCMCIA_SA1100_H) */ Index: drivers/pcmcia/sa1100_generic.c =================================================================== RCS file: /home/cvs/linux-nanoengine/drivers/pcmcia/sa1100_generic.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- drivers/pcmcia/sa1100_generic.c 9 May 2002 15:41:51 -0000 1.1.1.1 +++ drivers/pcmcia/sa1100_generic.c 9 May 2002 17:41:41 -0000 1.2 @@ -246,6 +246,10 @@ #ifdef CONFIG_SA1100_ADSBITSY pcmcia_low_level=&adsbitsy_pcmcia_ops; #endif + } else if (machine_is_nanoengine()) { +#ifdef CONFIG_SA1100_NANOENGINE + pcmcia_low_level = &nanoengine_pcmcia_ops; +#endif } if (!pcmcia_low_level) { Index: drivers/pcmcia/sa1100_nanoengine.c =================================================================== RCS file: drivers/pcmcia/sa1100_nanoengine.c diff -N drivers/pcmcia/sa1100_nanoengine.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ drivers/pcmcia/sa1100_nanoengine.c 25 Jul 2002 14:56:39 -0000 1.3 @@ -0,0 +1,154 @@ +/* + * drivers/pcmcia/sa1100_nanoengine.c + * + * PCMCIA implementation routines for NanoengineBoard + * Based off the Assabet. + * + * modified by Miguel Freitas + */ +#include +#include + +#include +#include +#include + +/* ready for socket 0 (active high)*/ +#define IRQ_GPIO_PC_READY0 IRQ_GPIO11 +#define GPIO_PC_READY0 GPIO_GPIO (11) + +/* ready for socket 1 (active high) */ +#define IRQ_GPIO_PC_READY1 IRQ_GPIO12 +#define GPIO_PC_READY1 GPIO_GPIO (12) + +/* detect for socket 0 (active low) */ +#define IRQ_GPIO_PC_CD0 IRQ_GPIO13 +#define GPIO_PC_CD0 GPIO_GPIO (13) + +/* detect for socket 1 (active low) */ +#define IRQ_GPIO_PC_CD1 IRQ_GPIO14 +#define GPIO_PC_CD1 GPIO_GPIO (14) + +/* reset socket 0 */ +#define GPIO_PC_RESET0 GPIO_GPIO (15) + +/* reset socket 1 */ +#define GPIO_PC_RESET1 GPIO_GPIO (16) + +static int nanoengine_pcmcia_init(struct pcmcia_init *init){ + int irq, res; + + printk( "nanoengine pcmcia support loaded\n" ); + + /* All those are inputs */ + GPDR &= ~(GPIO_PC_READY0|GPIO_PC_READY1|GPIO_PC_CD0|GPIO_PC_CD1); + + /* All those are outputs */ + GPDR |= (GPIO_PC_RESET0|GPIO_PC_RESET1); + + /* disable reset lines */ + GPCR = GPIO_PC_RESET0 | GPIO_PC_RESET1; + + /* Set transition detect */ + set_GPIO_IRQ_edge( GPIO_PC_READY0, GPIO_FALLING_EDGE ); + + set_GPIO_IRQ_edge( GPIO_PC_READY1, GPIO_FALLING_EDGE ); + + set_GPIO_IRQ_edge( GPIO_PC_CD0, GPIO_BOTH_EDGES ); + + set_GPIO_IRQ_edge( GPIO_PC_CD1, GPIO_BOTH_EDGES ); + + /* Register interrupts */ + irq = IRQ_GPIO_PC_CD0; + res = request_irq( irq, init->handler, SA_INTERRUPT, "PCMCIA_CD0", NULL ); + if( res < 0 ) goto irq_err; + + /* Register interrupts */ + irq = IRQ_GPIO_PC_CD1; + res = request_irq( irq, init->handler, SA_INTERRUPT, "PCMCIA_CD1", NULL ); + if( res < 0 ) goto irq_err; + + return 2; + +irq_err: + printk( KERN_ERR "%s: Request for IRQ %u failed\n", __FUNCTION__, irq ); + return -1; +} + +static int nanoengine_pcmcia_shutdown(void) +{ + free_irq( IRQ_GPIO_PC_CD0, NULL ); + free_irq( IRQ_GPIO_PC_CD1, NULL ); + + return 0; +} + +static int nanoengine_pcmcia_socket_state(struct pcmcia_state_array + *state_array){ + unsigned long levels; + + if(state_array->size!=2) return -1; + + memset(state_array->state, 0, + (state_array->size)*sizeof(struct pcmcia_state)); + + levels=GPLR; + + state_array->state[0].ready=(levels & GPIO_PC_READY0)?1:0; + state_array->state[0].detect=((levels & GPIO_PC_CD0)==0)?1:0; + state_array->state[0].bvd1=1; + state_array->state[0].bvd2=1; + state_array->state[0].wrprot=0; /* Not available */ + state_array->state[0].vs_3v=1; /* Can only apply 3.3V */ + state_array->state[0].vs_Xv=0; + + + state_array->state[1].ready=(levels & GPIO_PC_READY1)?1:0; + state_array->state[1].detect=((levels & GPIO_PC_CD1)==0)?1:0; + state_array->state[1].bvd1=1; + state_array->state[1].bvd2=1; + state_array->state[1].wrprot=0; /* Not available */ + state_array->state[1].vs_3v=1; /* Can only apply 3.3V */ + state_array->state[1].vs_Xv=0; + + return 1; +} + +static int nanoengine_pcmcia_get_irq_info(struct pcmcia_irq_info *info){ + + switch (info->sock) { + case 0: + info->irq=IRQ_GPIO_PC_READY0; + break; + case 1: + info->irq=IRQ_GPIO_PC_READY1; + break; + default: + return -1; + } + return 0; +} + +static int nanoengine_pcmcia_configure_socket(const struct pcmcia_configure + *configure) +{ + if(configure->sock>1) return -1; + + if(configure->reset) + GPSR = (configure->sock == 0) ? GPIO_PC_RESET0 : GPIO_PC_RESET1; + else + GPCR = (configure->sock == 0) ? GPIO_PC_RESET0 : GPIO_PC_RESET1; + + /* Silently ignore Vcc, Vpp, output enable, speaker enable. */ + + return 0; +} + +struct pcmcia_low_level nanoengine_pcmcia_ops = { + nanoengine_pcmcia_init, + nanoengine_pcmcia_shutdown, + nanoengine_pcmcia_socket_state, + nanoengine_pcmcia_get_irq_info, + nanoengine_pcmcia_configure_socket +}; +